1. Field of the Invention
This invention relates to the manufacture of semiconductor devices, in particular, dynamic random access memories (DRAMs) having shallow trench isolation (STI) vias for isolating the various transistors present within a capacitor array.
2. Description of Related Art
The use of silicon nitride (Si.sub.3 N.sub.4) liners in shallow trench isolations (STIs) have proven to be vital for eliminating silicon defects in trench-based DRAM at 0.25 .mu.m groundrules. With shrinking dimensions envisioned for the Gigabit generations, it is argued that a nitride liner, which can effectively block oxygen from penetrating into the trench storage capacitor, is a necessity. However, one drawback of the nitride liner presently used in the STI is its effect in trapping charge. Since the nitride liner sits close to the active silicon sidewalls, it has been shown to exacerbate (1) STI-bounded perimeter leakage, (2) node to P-well junction leakage, and most importantly, (3) buried P-channel field effect transistor (PFET) hot carrier degradation.
The proximity of the nitride liner to the active silicon sidewalls poses a serious limitation in the amount of thermal oxide that is initially grown in the STI (to heal etching-related damage). It has been observed that growing a thinner thermal oxide in the STI (i.e. less than 130 .ANG.) is beneficial in reducing dislocation formation. Indeed, it is extremely likely that future shrinks of the array cell will require that the thickness of the initial oxide grown in the STI be reduced to prevent dislocation generation. However, the PFET device has been shown to be severely degraded if the oxide between the silicon sidewalls and the nitride liner is less than 130 .ANG.. Thus, it is beneficial and desirable to maintain a certain distance between the silicon nitride liner and the active silicon sidewalls such that one minimizes parasitic leakages in the array and reduce PFET hot carrier degradation yet still able to block oxygen from diffusing into the trench capacitors.
U.S. Pat. No. 5,643,823 issued to Ho et al. and assigned to the assignee of the current invention discloses a crystalline silicon nitride liner in the shallow trench isolation as an oxygen barrier film. This reference, however, does not maintain a certain distance between the silicon nitride liner and the active silicon side walls such that parasitic leakages in the array are minimized in PFET hot carrier degradation.
U.S. Pat. No. 4,700,464 to Okada et al. discloses a process for forming U-shaped isolation grooves in a semiconductor body having silicon dioxide and silicon nitride films formed within the groove then filling the groove with a polycrystalline silicon topped with a silicon dioxide cap. The silicon nitride film absorbs the stresses produced by the expansion of the silicon dioxide cap preventing the development of dislocations. This reference teaches use of the silicon dioxide film to prevent short circuiting between the polycrystalline silicon in the U-grooves and the wiring formed on the surface of the substrate, or the electrodes formed in the vicinity of the wiring.
U.S. Pat. No. 5,492,858 to Bose et al. discloses the use of a silicon nitride liner conformally deposited on the thermally oxidized etched surfaces of an isolation trench. The nitride liner provides a more receptive surface than the thermal oxide coating to form a more durable bond with a later conformal dielectric filler and shields the underlying thermal oxide and or substrate from oxidation during subsequent processing. The nitride liner also serves to protect the silicon active areas from contamination during subsequent process steps since nitride is a better barrier than oxide. The reference is more precisely directed to using a silicon nitride liner to enhance subsequent processes such as planarizing the silicon substrate. It does not teach or suggest the use of the liner as a means for reducing parasitic leakages.
U.S. Pat. No. 5,516,721 to Galli et al. discloses an isolation structure using a liquid phase oxide material to fill the isolation structure. This reference does not teach nor suggest a silicon nitride liner in the isolation structure.
U.S. Pat. No. 5,604,159 to Cooper et al. discloses a method of making a contact structure or plug by etching vias into the silicon substrate. This reference does not teach nor suggest a silicon nitride liner within the contact structure to resolve the problem of parasitic leakages.
U.S. Pat. No. 5,719,085 to Moon et al. discloses a method of forming a trench isolation region by forming an opening in a semiconductor substrate, oxidizing the opening a first time and then etching the oxidized opening with a wet etch comprising hydrofluoric acid followed by oxidizing the opening a second time. This reference neither teaches nor discloses a silicon nitride liner in the shallow trench isolation structure.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a STI via having reduced parasitic leakages.
It is another object of the present invention to provide an STI via having reduced PFET hot carrier degradation.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.